The present invention relates in general to semiconductor technology, and more particularly to structures and methods for forming inter-electrode dielectrics (IEDs) and gate dielectrics in shielded gate trench field effect transistors (FETs).
Shielded gate trench FETs are advantageous over conventional FETs in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor without sacrificing on-resistance. Conventional shielded gate trench FETs include a shield electrode below a gate electrode. The shield and gate electrodes are insulated from each other by a dielectric layer referred to as an inter-electrode dielectric or IED. The gate electrode is insulated from its adjacent body regions by a gate dielectric. Conventional methods for forming the IED and gate dielectric include thermal oxidation and/or chemical vapor deposition (CVD) processes.
Conventional shielded gate trench FETs suffer from a number of drawbacks. The gate electrodes have sharp bottom corners that lead to high electric field, which may increase gate leakage. In addition, an IED or gate dielectric formed by thermal oxidation results in consumption of the mesa region between adjacent trenches and along the trench sidewalls, which leads to critical dimension (CD) loss. Also, an IED or gate dielectric formed by CVD has relatively high interface charges and dielectric trap charges, which increase leakage and reduce dielectric quality.
Thus, there is a need for structures and methods for forming shielded gate trench FETs with improved IED and gate dielectric layers.